Implementation of CRC and Viterbi algorithm on FPGA
نویسندگان
چکیده
Cyclic Redundancy Codes (CRC) code provides a simple, yet powerful, method for the detection of errors during digital data transmission and storage. Convolutional Coding and Decoding (CODEC) is a Forward Error Correction (FEC) technique that is particularly suited for a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN). The Viterbi Algorithm (VA) has been widely applied for decoding convolutionally encoded data in digital communication systems over the last 30 years. In this paper the implementation of CRC and Viterbi decoder on FPGA is presented. CRC-32 and Viterbi hard decision decoding algorithm for rate 1/2 implemented on FPGA. Also for higher SNR at the decoder side the concept of serially concatenated CRCConvolutional Coding (CC) with lookup table is also proposed. Keywords— CRC, FPGA, Viterbi, Trellis, Constraint length.
منابع مشابه
High Data Rate Pipelined Adaptive Viterbi Decoder Implementation
This paper presents a pipelined Adaptive Viterbi algorithm of rate 1⁄2 convolutional coding with a constraint length K = 3 which is designed in a reconfigurable hardware to take full advantage of algorithm parallelism, specialization and the throughput rate. In present work, the hardware implementation of the pipelined Adaptive Viterbi algorithm is performed using FPGA processor (Spartan-3AN st...
متن کاملConstraint Length Parametrizable Viterbi Decoder for Convolutional Codes
Convolutional codes are the widely used as Forward Error Correction (FEC) codes that are used in robust digital communication system. The parameterized implementation of a Viterbi decoder is presented in this paper where we can fix the constraint length for a code rate of 1 2 . This improves the decoding performance in area, accuracy and computational time. Viterbi algorithm is the widely emplo...
متن کاملFPGA Implementation of Viterbi Decoder using Trace back Architecture
Error correction is an integral part of any communication system and for this purpose, the convolution codes are widely used as forward error correction codes. For decoding of convolution codes, at the receiver end Viterbi Decoder is being employed. The parameters of Viterbi algorithm can be changed to suit a specific application. The high speed and small area are two important design parameter...
متن کاملFPGA Implementation of Soft Input Viterbi Decoder for CDMA2000 System
This paper presents a short overview of a soft input Viterbi decoder FPGA (Field-Programmable Gate Array) implementation for CDMA2000 (Code Division Multiple Access) wireless communication system in Verilog HDL (Hardware Description Language). The main goal of this project was resource-optimized implementation of the decoder on the target platform. It is well known that data transmissions over ...
متن کاملFPGA Implementation of Viterbi Decoder
Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. The Viterbi algorithm, which is the most extensively employed decoding algorithm for convolutional codes. In this paper, we present a field-programmable gate array impleme...
متن کامل